The present invention relates to semiconductor power device technology and more particularly to monolithically integrated trench FET and Schottky diode devices as well as trench MOS barrier Schottky (TMBS) rectifiers, and methods of manufacturing the same.
In power device structures where Schottky diode is integrated with a trench gate structure (e.g., TMBS rectifiers or monolithically integrated trench gate FET and Schottky diode devices), known Schottky contact etch techniques produce topologies that lead to poor barrier metal step coverage and high leakage current. These techniques are based on standard contact etch processes where selectivity to the underlying material is desirable. One such technique is shown in FIGS. 1A-1B.
As depicted in FIGS. 1A and 1B, in the Schottky diode region of the device, a selective dielectric etch is carried out to form the Schottky contact opening as defined by remaining dielectric portions 116. Because the resulting topography in the Schottky region is not suitable for forming the barrier metal, a selective soft etch of the silicon is carried out to improve the topology. However, the soft etch process: (1) adds another process step, (2) leads to the undercutting of source contact 132 thus bringing source metal closer to the channel region, and (3) adversely affects the metal fill characteristics of the source contact. Also, as can bee seen in FIG. 1B, while the topography is somewhat improved by the soft etch, the barrier metal 122 still has poor step coverage.
Thus, there is a need for a technique which significantly improves the topography in the Schottky contact area and minimizes the leakage current.